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ds2413 1-wire dual channel addressable switch general description the ds2413 is a dual-channel programmable i/o 1-wire ? chip. the pio outputs are configured as open-drain and provide up to 20ma continuous sink capability and off-state operating voltage up to 28v. control and sensing of the pio pins is performed with a dedicated device-level command protocol. to provide a high level of fault tolerance in the end application, the 1-wire io and pio pins are all capable of withstanding co ntinuous application of voltages up to 28v max. communication and operation of the ds2413 is performed with the single contact maxim/dallas 1-wire serial interface. applications ? led control ? accessory identification and control ? general purpose input/output ? key-pick systems ? industrial controllers ? system monitoring typical operating circuit px.y c r pup v cc local power r1 led switch r2 pioa io piob gnd ds2413 features ? open-drain programmable i/o pins ? pio pins support 20ma max continuous current sink ? supports 28v (max) pi o pin operating voltage ? on-resistance of pio pulldown transistor 20 ? max; off resistance 1m ? min ? parasitic power supply through 1-wire ? communicates to host with a single digital signal at 14.9kb or 100kbps using 1-wire protocol ? unique 64-bit rom serial number factory lasered into each device ? switchpoint hysteresis an d filtering to optimize performance in the presence of noise ? 1-wire io pin supports 28v absolute maximum dc level for fault conditions ? operates over a wide 1-wire voltage range of 2.8v to 5.25v from 0c to +70c ? high esd immunity of 1-wire io pin: 8kv hbm typical ? tsoc and tdfn packages available ordering information part temp range pin-package ds2413p+ 0c to +70c tsoc ds2413p+t&r 0c to +70c tsoc ds2413q+t&r 0c to +70c tdfn + denotes a lead(pb)-free package/rohs-compliant package. t&r = tape and reel. pin configuration w ww.maxim-ic.com commands, registers, and modes are capitalized for clarity. 1-wire is a registered trademark of maxim integrated products, inc. 19-5316; 7/10 1 2 3 6 5 4 2 413 y mrrf 6 5 4 1 2 3 ds 2413 ywwrr tsoc tdfn top view with marking. tdfn contacts not visible in this view. exposed paddle functional diagrams pin configurations appear at end of data sheet. functional diagrams continued at end of data sheet. ucsp is a trademark of maxim integrated products, inc. available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maxim integrated.com.
ds2413: 1-wire dual channel addressable switch 2 of 18 absolute maximum ratings voltage on any pin to gnd -0.5v, +30v maximum current into io pin ? 25ma maximum current into pio pin ? 30ma maximum current through gnd pins (both pins tied together) ? 60ma operating temperature range 0c to +70c junction temperature +150c storage temperature range -55c to +125c lead temperature (soldering, 10s) soldering temperature (reflow) +300c +260c stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of t he specifications is not implied. exposure to the absolute maximum rating condi tions for extended periods may affect device reliability. electrical characteristics t a = 0c to +70c parameter symbol conditions min typ max units io pin general data standard speed 2.8 5.25 overdrive speed 2.9 5.25 1-wire pullup voltage (note 1) v pup dc only; no 1-wire communication 28 v 1-wire pullup resistance r pup (notes 1, 2) 1.5 2.2 k? v pup ? 5.25v 3.5 70 v pup ? 3.30v 3.5 15 input load current i l v(io) = 28v (note 3) 400 950 a input capacitance c io at 25c (notes 4, 5) 800 pf input low voltage v il (notes 1, 6) 0.4 v high-to-low switching threshold v tl (notes 5, 7, 8) 0.4 3.2 v low-to-high switching threshold v th (notes 5, 7, 9) 0.7 3.6 v switching hysteresis v hy (notes 5, 10) 0.2 v output low voltage v ol at 4ma current load (note 11) 0.4 v standard speed, r pup = 2.2k ? 5 overdrive speed, r pup = 2.2k ? 2 recovery time (notes 1, 12) t rec overdrive speed, directly prior to reset pulse; r pup = 2.2k ? 5 s standard speed 0.5 5.0 rising-edge hold-off time (notes 5, 13) t reh overdrive speed not applicable (0) s standard speed, v pup ? 4.5v 65 standard speed (note 14) 67 overdrive speed, v pup ? 4.5v (note 14) 9 time slot duration (note 1, 5) t slot overdrive speed (note 14) 10 s io pin, 1-wire reset, presence detect cycle standard speed, v pup ? 4.5v 480 960 standard speed (note 14) 600 960 overdrive speed, v pup ? 4.5v 48 80 reset low time (note 1) t rstl overdrive speed (note 14) 63 80 s standard speed, v pup ? 4.5v 15 66 standard speed 15 68 overdrive speed, v pup ? 4.5v 2 7.0 presence detect high time (notes 14, 15) t pdh overdrive speed 2 8.2 s standard speed, v pup > 4.5v 0.24 1.4 standard speed 0.24 1.6 overdrive speed, v pup ? 4.5v 0 0.7 presence detect fall time (notes 5, 16) t fpd overdrive speed 0 0.9 s standard speed, v pup > 4.5v 60 240 standard speed (note 14) 60 260 overdrive speed, v pup ? 4.5v (note 14) 8 25 presence detect low time (note 15) t pdl overdrive speed (note 14) 8 32 s
ds2413: 1-wire dual channel addressable switch 3 of 18 parameter symbol conditions min typ max units standard speed, v pup > 4.5v 67.4 75 standard speed 69.6 75 overdrive speed, v pup ? 4.5v 7.7 10 presence detect sample time (notes 1, 20) t msp overdrive speed 9.1 10 s io pin, 1-wire write standard speed, v pup > 4.5v 60 120 standard speed (note 14) 62 120 overdrive speed, v pup ? 4.5v (note 14) 7 16 write-0 low time (notes 1, 17) t w0l overdrive speed (note 14) 8 16 s standard speed 5 15 write-1 low time (notes 1, 17) t w1l overdrive speed 1 2 s io pin, 1-wire read standard speed 5 15 - ? read low time (notes 1, 18) t rl overdrive speed 1 2 - ? s standard speed t rl + ? 15 read sample time (notes 1, 18) t msr overdrive speed t rl + ? 2 s pio pins leakage current i lp pin at 28v (note 19) 8.5 24 a input capacitance c p (note 5) 100 pf output low voltage v olp 20ma load current 0.4 v input low voltage v ilp (note 1) 0.8 v input high voltage (note 21) v ihp (note 1) v pup ? 0.3v 28 v note 1: system requirement. note 2: full r pup range guaranteed by design and simulation. not produc tion tested. production testing performed at a fixed r pup value. maximum allowable pullup resistance is a func tion of the number of 1-wire devices in the system and 1-wire recovery times. the specified value here applies to systems with only one device and with the minimum 1-wire recovery times. for more heavily loaded systems, an active pullup such as that found in the ds2482-x00 or ds2480b may be required. the ds2482-x00 may not always detect the ds2413 presence pulse. for proper operation it may be necessary to disregard (force to 1) the ppd bit in the ds2482-x00 status register. note 3: the i-v characteristic is linear for voltages greater than 10v. note 4: capacitance on the data pin could be 800pf when v pup is first applied. if a 2.2k ? resistor is used to pull up the data line, 2.5s after v pup has been applied the parasite capacitance will not affect normal communications. note 5: guaranteed by design and simulation. not production tested. note 6: the voltage on io needs to be less than or equal to v ilmax whenever the master drives the line low. note 7: v tl and v th are functions of the internal suppl y voltage, which is a function of v pup and the 1-wire recovery times. the v th and v tl maximum specifications are valid at v pupmax (5.25v). in any case, v tl < v th < v pup . note 8: voltage below which, during a falling edge on io, a logic 0 is detected. note 9: voltage above which, during a rising edge on io, a logic 1 is detected. note 10: after v th is crossed during a rising edge on io, the voltage on io has to drop by at least v hy to be detected as logic '0'. note 11: the i-v characteristic is linear for voltages less than 1v. note 12: applies to a single ds2413 attached to a 1-wire line. note 13: the earliest recognition of a negative edge is possible at t reh after v th has been previously reached. note 14: highlighted numbers are not in compliance with legacy 1-wire product standards. see comparison table below. note 15: t pdh is deemed to have ended when the voltage on io drops below 80% of v pup on the leading edge of the presence-detect low pulse. t pdl is deemed to have begun when the voltage on io drops below 20% of v pup on the leading edge of the pulse. note 16: interval during the negative edge on io at the beginning of a presence detect pulse between the time at which the voltage is 80% of v pup and the time at which the voltage is 20% of v pup . note 17: ? in figure 12 represents the time required for the pullup circuitry to pull the voltage on io up from v il to v th . the actual maximum duration for the master to pull the line low is t w1lmax + t f - ? and t w0lmax + t f - ? respectively. note 18: ? in figure 12 represents the time required for the pullup circuitry to pull the voltage on io up from v il to the input high threshold of the bus master. the actual maximum duration for the master to pull the line low is t rlmax + t f . note 19: the i-v characteristic is linear for voltages greater than 7v. note 20: t msp is a system required sample point and not directly producti on tested. production testing is performed on related parameters t pdh and t pdl . parameter t fpd is guaranteed by design and simulation, not production tested. note 21: production tested for v ihp(min) . v ihp(max) is guaranteed by design and simulation, not production tested.
ds2413: 1-wire dual channel addressable switch 4 of 18 legacy values ds2413 values parameter standard speed overdrive speed standard speed overdrive speed min max min max min max min max t slot (incl. t rec ) 61s (undef.) 7s (undef.) 67s (undef.) 10s (undef.) t rstl 480s (undef.) 48s 80s 600s 960s 63s 80s t pdh 15s 60s 2s 6s 15s 68s 2s 8.2s t pdl 60s 240s 8s 24s 60s 260s 8s 32s t w0l 60s 120s 6s 16s 62s 120s 8s 16s pin description name tsoc pin # tdfn pin # function io 2 2 1-wire bus interface. open-drain , requires external pullup resistor. pioa 6 4 programmable i/o pin, open-dr ain with weak pulldown, power-on default is off (pioa = 1). piob 4 6 programmable i/o pin, open-dr ain with weak pulldown, power-on default is off (piob = 1). gnd1 1 3 ground reference 1 gnd2 5 5 ground reference 2; both gnd pins must be connected in the application. nc 3 1 not connected gnd ? ep exposed paddle (tdfn only). solder evenly to the board?s ground plane for proper operation. see application note 3273 for additional information. description the ds2413 combines two pio pins and a fully featured 1- wire interface in a single chip. pio outputs are open- drain, operate at up to 28v and provide an on resistance of 20 ? max. a robust communication protocol ensures that pio output changes occu r error-free. each ds2413 has a registration number that is 64 bits long. the registration number guarantees unique identification and is used to addre ss the device in a multidrop 1-wire network environment, where multiple devices reside on a common 1-wire bus and operate independently of each other. device power is supplied parasitic ally from the 1-wire bus. the ds2413? s applications of include accessory identification and control, system monito ring, and general-purpose input/output. overview the block diagram in figure 1 shows the relationships between the major sections of the ds2413. the ds2413 has two main components: 64-bit registration number, and pi o control. the hierarchical structure of the 1-wire protocol is shown in figure 2. the bus master must first provide one of the seven rom function commands, 1) read rom, 2) match rom, 3) search rom, 4) skip rom, 5) resume, 6) overdrive-skip rom or 7) overdrive- match rom. upon completion of an overdrive rom command byte executed at standard speed, the device enters overdrive mode where all subsequent co mmunication occurs at a higher speed. the protocol required for these rom function commands is described in figure 10. a fter a rom function command is successfully executed, the pio functions become accessible and the master ma y provide one of the two pio function commands. the protocol for these commands is described in figure 6. all data is read and written least significant bit first. figure 1. block diagram 1-wire interface pio control 64-bit registration number pioa io internal v dd piob
ds2413: 1-wire dual channel addressable switch 5 of 18 64-bit lasered rom each ds2413 has a unique rom registration number that is 64 bits long, as shown in figure 3. the first eight bits are a 1-wire family code. the next 48 bits are a uni que serial number. the last eight bits are a crc (cyclic redundancy check) of the first 56 bits. the 1-wire crc is generated using a polynomial generator consisting of a shift register and xor gates as shown in figure 4. the polynomial is x 8 + x 5 + x 4 + 1. additional information about the dallas 1-wire crc is available in application note 27 . the shift register bits are initialized to zero. then starting with the lsb of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, then the serial number is entered. after the 48th bit of the serial number has been entered, the shift register contains the crc value. shifting in the eight bits of crc should return the shift register to all zeros. figure 2. hierarchical stru cture for 1-wire protocol ds2413 command level: 1-wire rom function commands (see figure 10) ds2413-specific pio function commands (see figure 6) available commands: read rom match rom search rom skip rom resume overdrive skip overdrive match pio access read pio access write data field affected: 64-bit reg. #, rc-flag 64-bit reg. #, rc-flag 64-bit reg. #, rc-flag rc-flag rc-flag rc-flag, od-flag 64-bit reg. #, rc-flag, od-flag pio pins pio pins command codes: 33h 55h f0h cch a 5h 3ch 69h f5h 5ah figure 3. 64-bit lasered rom msb lsb 8-bit crc code 48-bit serial number 8-bit family code (3ah) msb lsb msb lsb msb lsb figure 4. 1-wire crc generator x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 polynomial = x 8 + x 5 + x 4 + 1 1 st stage 2 nd stage 3 rd stage 4 th stage 6 th stage 5 th stage 7 th stage 8 th stage input data
ds2413: 1-wire dual channel addressable switch 6 of 18 pio stucture each pio consists of an open-drain pull down transistor with 28v capability. th e transistor is controlled by the pio output latch, as shown in figure 5. the pio control unit connects the pios to the 1-wire interface. figure 5. pio simplified logic diagram pio pin state pio pin pio out- p ut latch pio output latch state. q d q pio data pio clock clock pio function commands the pio function flow chart (figure 6) describes the protocols necessary to access the pio pins of the ds2413. examples on how to use these functions are included at the end of this document. the communication between master and ds2413 takes place either at standard speed (default, od = 0) or at overdrive speed (od = 1). if not explicitly set into the overdrive mode, the ds2413 powers up in standard speed. pio access read [f5h] this command reads the pio logical status and reports it together with the state of the pio output latch in an endless loop. a pio access read can be terminated at any time with a 1-wire reset. pio status bit assignment b7 b6 b5 b4 b3 b2 b1 b0 complement of b3 to b0 piob output latch state piob pin state pioa output latch state pioa pin state the state of both pio channels is sampled at the same ti me. the first sampling occurs during the last (most significant) bit of the command code f5h. the pio status is then reported to the bus master. while the master receives the last (most significant) bi t of the pio status byte, the next samp ling occurs and so on until the master generates a 1-wire reset. the sampling occurs with a delay of t reh +x from the rising edge of the ms bit of the previous byte, as shown in figure 7. the value of "x" is approximately 0.2s. figure 7. pio access read timing diagram io ms 2 bits of previous byte ls 2 bits of pio status byte v th sampli ng point t reh +x notes: 1 the "previo us byte" could be the command code or the data byte resulting from the previous pio sample. 2 the sample point timing also applies to the pio acce ss write command, with the "previous byte" being the write confirmation byte (aah).
ds2413: 1-wire dual channel addressable switch 7 of 18 figure 6. pio function flow chart to rom functions flow chart (figure 10) bus master tx memory function command from rom functions flow chart (figure 10) y f5h pio access read? y n master tx reset? bus master rx pio pin status y n 5ah pio access write? bus master tx new pio output data byte bus master tx inverted new pio output data b y te transmission ok? ds2413 updates pio output latch bus master rx confirmation aah ds2413 samples pio pin status bus master rx pio pin status y n master tx reset? n y bus master rx ?1?s y n master tx reset? note 1) see the command description for the exact timing of the pio pin sampling and updating. n y ds2413 samples pio pin status 1 ) 1 ) 1 )
ds2413: 1-wire dual channel addressable switch 8 of 18 pio access write [5ah] the pio access write command writes to the pio output la tches, which control the pulldown transistors of the pio channels. in an endless loop this command first writes new data to the pio and then reads back the pio status. this implicit read-after-write can be used by the master for status verification. a pio access write can be terminated at any time with a 1-wire reset. pio output data bit assignment b7 b6 b5 b4 b3 b2 b1 b0 x x x x x x piob pioa after the command code the master tran smits a pio output data byte that determines the new state of the pio output transistors. the first (least significant) bit is associat ed to pioa; the next bit affects piob. the other 6 bits of the new state byte do not have corresponding pio pins. these bits should always be transmitted as "1"s. to switch the output transistor on, the corresponding bit value is 0. to switch the out put transistor off (non-conducting) the bit must be 1. this way the bit transmitted as the new pi o output state arrives in its true form at the pio pin. to protect the transmission against data errors, the master must repeat the pio output data byte in its inverted form. only if the transmission was error-free will the pio status change. the actual pio transition to the new state occurs with a delay of t reh +x from the rising edge of the ms bit of the inve rted pio byte, as shown in figure 8. the value of "x" is approximately 0.2s. to inform the master about the successful communica tion of the pio byte, the ds2413 transmits a confirmation byte with the data pattern aah. while the ms bit of the confirmation byte is transmitted, the ds2413 samples the state of the pio pins, as shown in figure 7, and sends it to the master. the master can either continue writing more data to t he pio or issue a 1-wire reset to end the command. figure 8. pio access write timing diagram io pio ms 2 bits of inverted pio output data byte ls 2 bits of confir- mation byte (aah) v th t reh +x 1-wire bus system the 1-wire bus is a system that has a single bus master and one or more slaves. in all instances the ds2413 is a slave device. the bus master is typically a microcontroller. the discussion of this bus system is broken down into three topics: hardware configuration, transaction sequen ce, and 1-wire signaling (signal types and timing). the 1-wire protocol defines bus transactions in terms of the bus state during specif ic time slots, which are initiated on the falling edge of sync pulses from the bus master. hardware configuration the 1-wire bus has only a single line by definition; it is impo rtant that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attach ed to the 1-wire bus must have open-drain or tri-state outputs. the 1-wire port of the ds2413 is open drain with an in ternal circuit equivalent to that shown in figure 9. a multidrop bus consists of a 1-wire bus with multip le slaves attached. the ds2413 supports both a standard and overdrive communication speed of 14.9kbps (max) and 100 kbps (max), respectively. note that legacy 1-wire products support a standard communication speed of 16.3k bps and overdrive of 142kbps. the value of the pullup resistor primarily depends on the network size and load co nditions. the ds2413 requires a pullup resistor of 2.2k ? (max) at any speed.
ds2413: 1-wire dual channel addressable switch 9 of 18 the idle state for the 1-wi re bus is high. if for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 16s (overdrive speed) or more than 120s (standard speed), one or more devices on the bus may be reset. figure 9. hardware configuration open drain port pin rx = receive tx = transmit 100 ? mosfet v pup rx tx tx rx data r pup i l bus master ds2413 1-wire port transaction sequence the protocol for accessing the ds2413 th rough the 1-wire port is as follows: ? initialization ? rom function command ? pio function command ? data initialization all transactions on the 1-wire bus begin with an initializat ion sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presen ce pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the ds2413 is on t he bus and is ready to operate. for more details, see the 1- wire signaling section. 1-wire rom func tion commands once the bus master has detected a presence, it can is sue one of the seven rom function commands that the ds2413 supports. all rom function commands are 8 bits long. a list of these commands follows (refer to the flow chart in figure 10). read rom [33h] this command allows the bus master to read the ds2413?s 8-bit family code, unique 48-bit serial number, and 8-bit crc. this command can only be used if there is a single slave on the bus. if more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-and result). the resultant family code and 48-bit seri al number result in a mismatch of the crc. match rom [55h] the match rom command, followed by a 64-bit rom seq uence, allows the bus master to address a specific ds2413 on a multidrop bus. only the ds2413 that exac tly matches the 64-bit rom sequence, including the external address, responds to the following pio function command. all other slaves wait for a reset pulse. this command can be used with a single or multiple devices on the bus.
ds2413: 1-wire dual channel addressable switch 10 of 18 search rom [f0h] when a system is initially brought up, the bus master might not know the nu mber of devices on the 1-wire bus or their device id numbers. by taking advantage of the wir ed-and property of the bus, the master can use a process of elimination to identify the device id numbers of all slav e devices. for each bit of the device id number, starting with the least significant bit, the bus master issues a triplet of time slots. on the first slot, each slave device participating in the search out puts the true value of its device id number bit. on the second slot, each slave device participating in the search outputs the complemented value of its device id number bit. on the third slot, the master writes the true value of the bit to be selected. all slave devices that do not match the bit written by the master stop participating in the search. if both of the read bits are ze ro, the master knows that slave devices exist with both states of the bit. by choosing which state to write, t he bus master branches in the rom code tree. after one complete pass, the bus master knows the device id num ber of a single device. additional passes identify the device id numbers of the remaining devices. refer to application note 187: 1-wire search algorithm for a detailed discussion, including an example. since with the ds2413 th e rom crc is not valid if one or more address inputs are tied to gnd, it is recommended to do a double search when building a list of devices on the 1-wire line. skip rom [cch] this command can save time in a single-drop bus system by allowing the bus master to access the pio functions without providing the 64-bit rom code. if more than one slave is present on the bu s and, for example, a read command is issued following the skip rom command, data co llision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-and result). resume [a5h] to maximize the data throughput in a multidrop environm ent, the resume function is available. this function checks the status of the rc bit and, if it is set, directly transfers control to the pio func tions, similar to a skip rom command. the only way to set the rc bit is through succ essfully executing the matc h rom, search rom, or overdrive match rom command. once the rc bit is se t, the device can repeatedly be accessed through the resume command function. accessing another device on t he bus clears the rc bit, preventing two or more devices from simultaneously responding to the resume command function. overdrive skip rom [3ch] on a single-drop bus this command can save time by allo wing the bus master to access the pio functions without providing the 64-bit rom code. unlike the normal skip rom command, the overdrive skip rom sets the ds2413 in the overdrive mode (od = 1). all communication following this command has to occur at overdrive speed until a reset pulse of minimum 480s duration resets all devices on the bus to standard speed (od = 0). when issued on a multidrop bus, this command sets all overdrive-supporting devices into overdrive mode. to subsequently address a specific over drive-supporting device, a reset pulse at overdrive speed has to be issued followed by a match rom or search rom command sequence . this speeds up the time for the search process. if more than one slave supporting overdr ive is present on the bus and the overdrive skip rom command is followed by a read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-and result). overdrive match rom [69h] the overdrive match rom command followed by a 64-bit ro m sequence transmitted at overdrive speed allows the bus master to address a specific ds2413 on a multidro p bus and to simultaneously set it in overdrive mode. only the ds2413 that exactly matches the 64-bit rom sequence responds to the subsequent pio function command. slaves already in overdrive mode from a prev ious overdrive skip or successful overdrive match command remain in overdrive mode. all overdrive-capable slaves return to standard speed at the next reset pulse of minimum 480s duration. the overdrive match rom comm and can be used with a single or multiple devices on the bus.
ds2413: 1-wire dual channel addressable switch 11 of 18 figure 10-1. rom functions flow chart from figure 10 2 nd part to pio functions flow chart (figure 6) master tx bit 0 master tx bit 63 master tx bit 1 bit 63 match ? rc = 0 ds2413 tx bit 0 ds2413 tx bit 0 master tx bit 0 ds2413 tx bit 1 ds2413 tx bit 1 master tx bit 1 ds2413 tx bit 63 ds2413 tx bit 63 master tx bit 63 rc = 1 bit 1 match ? bit 0 match ? y n y n y n bit 63 match ? rc = 0 rc = 1 bit 1 match ? bit 0 match ? y n y n y n rc = 0 ds2413 tx crc byte ds2413 tx serial number (6 bytes) ds2413 tx family code (1 byte) rc = 0 to figure 10 2 nd part n f0h search rom command ? n 55h match rom command ? n cch skip rom command ? y y y y n 33h read rom command ? to figure 10 2 nd part from pio functions flow chart (figure 6) bus master tx rom function command ds2413 tx presence pulse od reset pulse ? n y od = 0 bus master tx reset pulse from figure 10, 2 n d par t
ds2413: 1-wire dual channel addressable switch 12 of 18 figure 10-2. rom functions flow chart (continued) to figure 10 1 st part from figure 10 1 st part from figure 10 1 st part to figure 10, 1 s t part y n a5h resume command ? rc = 1 ? y n 3ch overdrive skip rom ? rc = 0 ; od = 1 master tx reset ? y n n y master tx reset ? n y master tx bit 0 master tx bit 63 master tx bit 1 bit 63 match ? rc = 0 ; od = 1 rc = 1 bit 1 match ? y n y n bit 0 match ? y n y n 69h overdrive match rom ?
ds2413: 1-wire dual channel addressable switch 13 of 18 1-wire signaling the ds2413 requires strict protocols to ensure data integrity. the protocol cons ists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write-zero, write-one, and read-data. except for the presence pulse, the bus master initiates all fa lling edges. the ds2413 can communicate at two different speeds, standard speed, and overdriv e speed. if not explicitly set in to the overdrive mode, the ds2413 communicates at standard speed. while in overdriv e mode the fast timing applies to all waveforms. to get from idle to active, the voltage on the 1-wire line needs to fall from v pup below the threshold v tl . to get from active to idle, the voltage needs to rise from v ilmax past the threshold v th . the time it takes for the voltage to make this rise is seen in figure 11 as ' ? ' and its duration depends on the pullup resistor (r pup ) used and the capacitance of the 1-wire network attached. the voltage v ilmax is relevant for the ds2413 when determining a logical level, not triggering any events. figure 11 shows the initialization sequence required to begin any communication with the ds2413. a reset pulse followed by a presence pulse indicates the ds2413 is ready to receive data, given the correct rom and pio function command. if the bus master uses slew-rate c ontrol on the falling edge, it must pull down the line for t rstl + t f to compensate for the edge. a t rstl duration of 480s or longer exits the overdrive mode, returning the device to standard speed. if the ds2413 is in overdrive mode and t rstl is no longer than 80s, the device remains in overdrive mode. if the device is in overdrive mode and t rstl is between 80s and 480s, the device will reset, but the communication speed is undetermined. figure 11. initialization proced ure: reset and presence pulse resistor master ds2413 t rstl t pdl t rsth t pdh master tx ?reset pulse? master rx ?presence pulse? v pup v ihmaster v th v tl v ilmax 0v ? t f t rec t msp after the bus maste r has released the line it goes into receive mode. now the 1-wire bus is pulled to v pup through the pullup resistor, or in case of a ds2482-x00 or ds2480b driver, by active circuitry. when the threshold v th is crossed, the ds2413 waits for t pdh and then transmits a presence pulse by pulling the line low for t pdl . to detect a presence pulse, the master must test th e logical state of the 1-wire line at t msp . the t rsth window must be at least the sum of t pdhmax , t pdlmax , and t recmin . immediately after t rsth is expired, the ds2413 is ready for data communication. in a mixed population network, t rsth should be extended to minimum 480s at standard speed and 48s at overdrive speed to accommodate other 1-wire devices.
ds2413: 1-wire dual channel addressable switch 14 of 18 read/write time slots data communication with the ds2413 takes place in time slots, which carry a single bit each. write-time slots transport data from bus master to slav e. read-time slots transfer data from slave to master. figure 12 illustrates the definitions of the writ e- and read-time slots. all communication begins with the master pulling the data lin e low. as the voltage on the 1-wire line falls below the threshold v tl , the ds2413 starts its internal timing generator t hat determines when the data line is sampled during a write-time slot and how long data is valid during a read-time slot. figure 12. read/write timing diagram write-one time slot resistor master v pup v ihmaster v th v tl v ilmax 0v t f t slot t w1l ? write-zero time slot resistor master t rec v pup v ihmaster v th v tl v ilma x 0v t f t slot t w0l ? read-data time slot resistor master ds2413 t rec v pup v ihmaster v th v tl v ilmax 0v master sampling window ? t f t slot t rl t msr
ds2413: 1-wire dual channel addressable switch 15 of 18 master-to-slave for a write-one time slot, the voltage on the data line must have crossed the v th threshold before the write-one low time t w1lmax is expired. for a write-zero time slot, the voltage on the data line must stay below the v th threshold until the write-zero low time t w0lmin is expired. for the most reliable communication, the voltage on the data line should not exceed v ilmax during the entire t w0l or t w1l window. after the v th threshold has been crossed, the ds2413 needs a recovery time t rec before it is ready for the next time slot. slave-to-master a read-data time slot begins like a write-one time slot. the voltage on the data line must remain below v tl until the read low time t rl is expired. during the t rl window, when responding with a 0, the ds2413 starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. when responding with a 1, the ds2413 does not hold the data li ne low at all, and the voltage starts rising as soon as t rl is over. the sum of t rl + ? (rise time) on one side and the internal timing generator of the ds2413 on the other side define the master sampling window (t msrmin to t msrmax ) in which the master must perform a read from the data line. for the most reliable communication, t rl should be as short as permissible, and the master should read close to but no later than t msrmax . after reading from the data line, the master must wait until t slot is expired. this guarantees sufficient recovery time t rec for the ds2413 to get ready for the next time slot. note that t rec specified herein applies only to a single ds2413 attached to a 1- wire line. for multidevice configurations, t rec needs to be extended to accommodate the additional 1-wire device input c apacitance. alternatively, an interface that performs active pullup during the 1-wire recovery time such as the ds2482-x00 or ds2480b 1 -wire line drivers can be used. improved network behavior (switchpoint hysteresis) in a 1-wire environment, line termination is possible onl y during transients controlled by the bus master (1-wire driver). 1-wire networks, therefore, are susceptible to noise of vari ous origins. depending on the physical size and topology of the network, reflections from end points and br anch points can add up, or cancel each other to some extent. such reflections are visible as glitches or ringi ng on the 1-wire communication line. noise coupled onto the 1-wire line from external sources can also result in signal glitching. a glitch dur ing the rising edge of a time slot can cause a slave device to lose synchronization with the mast er and, consequently, result in a search rom command coming to a dead end or cause a device-specific functi on command to abort. for better performance in network applications, the ds2413 uses a new 1-wire front end, whic h makes it less sensitive to noise and also reduces the magnitude of noise injected by the slave device itself. the 1-wire front end of the ds2413 differs from traditional slave devices in four characteristics. 1) the falling edge of the presence pulse has a controlled slew rate. this provides a better match to the line impedance than a digitally switched transistor, converti ng the high-frequency ringing known from traditional devices into a smoother low-bandwidth transition. the slew-rate control is specified by the parameter t fpd , which has different values for standard and overdrive speed. 2) there is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a time slot. this reduces the sensitivity to high-frequency noise. this additional filtering does not apply at overdrive speed. 3) there is a hysteresis at the low-to-high switching threshold v th . if a negative glitch crosses v th but does not go below v th - v hy , it will not be recognized (figure 13, case a). the hysteresis is effective at any 1-wire speed. 4) there is a time window specified by the rising edge hold-off time t reh during which glitches are ignored, even if they extend below v th - v hy threshold (figure 13, case b, t gl < t reh ). deep voltage droops or glitches that appear late after crossing the v th threshold and extend beyond the t reh window cannot be filtered out and are taken as the beginning of a new time slot (figure 13, case c, t gl ? t reh ). devices that have the parameters t fpd , v hy , and t reh specified in their electrical characteristics use the improved 1- wire front end.
ds2413: 1-wire dual channel addressable switch 16 of 18 figure 13. noise suppression scheme v pup v th v hy 0v t reh t gl t reh t gl case a case c case b command-specific 1-wire co mmunication pr otocol?legend symbol description rst 1-wire reset pulse generated by master. pd 1-wire presence pulse generated by slave. select command and data to satisfy the rom function protocol. pior command "pio access read". piow command "pio access write". ff loop indefinite loop where the master reads ff bytes. command-specific 1-wi re communication prot ocol?color codes master to slave slave to master pio access read (cannot fail) rst pd select pior continues until master sends reset pulse pio access write (success) rst pd select piow loop until master sends reset pulse pio access write ( invalid data byte ) rst pd select piow ff loop
ds2413: 1-wire dual channel addressable switch 17 of 18 pio access read example read the state of the pios 3 times. with only a single ds2413 connected to the bus master, the communication looks like this: master mode data (lsb first) comments tx (reset) reset pulse rx (presence) presence pulse tx cch issue ?skip rom? command tx f5h issue ?pio access read? command rx <3 data bytes> read 3 pio samples tx (reset) reset pulse rx (presence) presence pulse pio access write example set both pios to 0 and then set pioa to 1. both pios are pulled high to v cc or v pup by a resistor. with only a single ds2413 connected to the bus master, the communication looks like this: master mode data (lsb first) comments tx (reset) reset pulse rx (presence) presence pulse tx cch issue ?skip rom? command tx 5ah issue ?pio access write? command tx fch write new pio output state tx 03h write inverted new pio output state rx aah read confirmation byte rx f0h read new pio pin status tx fdh write new pio output state tx 02h write inverted new pio output state rx aah read confirmation byte rx c3h read new pio pin status tx (reset) reset pulse rx (presence) presence pulse note : usually, the pio pin state and pio ou tput latch state are the same. to read from a pio, the pio output latch must be 1. if the pio pin is then pulled low by a sw itch or external circuitry, the output latch state and pin state are different. package information for the latest package outline information, go to www.maxim-ic.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package draw ings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code document no. land pattern 6 tsoc d6+1 21-0382 90-0321 6 tdfn t633+2 21-0137 90-0058
ds2413: 1-wire dual channel addressable switch revision history revision date description pages changed 11/07 ? remove epsilon from the tw1l spec in the ec table . ? apply ec table note 17 also to twol . ? add to ec table notes 17 and 18 the reference to figure 12 and the text "the actual maximum duration...." ? show epsilon also in the write zero time slot graphic. ? add note that the v th and v tl maximum spec values apply at v pup max (v th and v tl are gbd, not tested). ? added 3mm x 3mm x 0.8mm tdfn package. ? lf update, delete standard versions (with lead) from ordering info. ? added package information table. 1, 3, 4, 14, 17, 18 11/08 ? added ?tdfn packages available? within the features section. ? added new tdfn part number ?ds2413q+t&r,? and information to the ordering information table. ? removed the note to ?contact factory for availability of the tdfn package? from the ordering information table. 1 07/10 ? changed soldering temperature from jedec reference to explicit values. ? added ds2482-related application hints to ec table, note 2. ? removed reference to the ds2490. ? added land pattern reference. 2?3, 17 18 maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. ? 2010 maxim integrated the maxim logo and maxim integrated are trademarks of maxim integrated products, inc.

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